80960JA Datasheet, PDF (16/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
3.1
3.1.1
Table 2.
Pin Descriptions
This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)
package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid
Array (MPBGA).
Section 3.1.1, “Functional Pin Definitions”, describes pin function; Section 3.1.2, “80960Jx
132-Lead PGA Pinout”, Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” and Section 3.1.4,
“80960Jx 196-Ball MPBGA Pinout”, define the signal and pin locations for the supported package
types.
Functional Pin Definitions
Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with
the bus interface are described in Table 3. Pins associated with basic control and test functions are
described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.
Pin Description Nomenclature
Symbol
Description
I
O
I/O
–
S
A (...)
R (...)
H (...)
P (...)
Input pin only.
Output pin only.
Pin can be either an input or output.
Pin must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to CLKIN.
A(E) Edge sensitive input
A(L) Level sensitive input
While the processor’s RESET pin is asserted, the pin:
R(1) is driven to V_CC
R(0) is driven to V_SS
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to V_CC
While the processor is in the hold state, the pin:
H(1) is driven to V_CC
H(0) is driven to V_SS
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
While the processor is halted, the pin:
P(1) is driven to V_CC
P(0) is driven to V_SS
P(Q) Maintains previous state or continues to be a valid output
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