80960MC Datasheet, PDF (8/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

80960MC
Control
Opcode
Displacement
Compare and
Branch
Opcode Reg/Lit
Reg
M
Displacement
Register to
Register
Opcode
Reg
Reg/Lit
Modes
Ext’d Op
Reg/Lit
Memory Access-
Opcode
Reg
Base M
X
Short
Offset
Memory Access- _Opcode
Reg
Long
Base
Mode
Displacement
Scale xx Offset
Figure 2. Instruction Formats
1.1.1 Memory Space And Addressing Modes
The 80960MC allows each task (process) to address
a logical memory space of up to 4 Gbytes. Each
task’s address space is divided into four 1 Gbyte
regions and each region can be mapped to physical
addresses by zero, one, or two levels of page tables.
The region with the highest addresses (Region 3) is
common to all tasks.
In keeping with RISC design principles, the number
of addressing modes is minimal yet includes all
those necessary to ensure efficient execution of
high-level languages such as Ada, C, and Fortran.
Table 2 lists the memory accessing modes.
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) + 32-
Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
1.1.2 Data Types
The 80960MC recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
• 32-, 64- and 80-bit real numbers
Non-Numeric:
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3 Large Register Set
The 80960MC programming environment includes a
large number of registers. 36 registers are available
at any time; this greatly reduces the number of
memory accesses required to perform algorithms,
which leads to greater instruction processing speed.
Two types of general-purpose registers are avail-
able: local and global. The 20 global registers
consist of sixteen 32-bit registers (G0 though G15)
and four 80-bit registers (FP0 through FP3). These
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PRELIMINARY