80960MC Datasheet, PDF (11/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

80960MC
Table 3. Sample Floating-Point Execution Times
(µs) at 25 MHz
Function
Add
Subtract
Multiply
Divide
32-Bit
0.4
0.4
0.7
1.3
64-Bit
0.5
0.5
1.3
2.9
Square Root
3.7
Arctangent
10.1
Exponent
11.3
Sine
15.2
Cosine
15.2
3.9
13.1
12.5
16.6
16.6
1.1.9 Multitasking Support
Multitasking programs commonly involve the moni-
toring and control of an external operation, such as
the activities of a process controller or the move-
ments of a machine tool. These programs generally
consist of a number of processes that run indepen-
dently of one another, but share a common
database or pass data among themselves.
The 80960MC offers several hardware functions
designed to support multitasking systems. One
unique feature, called self-dispatching, allows a
processor to switch itself automatically among
scheduled tasks. When self-dispatching is used, all
the operating system is required to do is place the
task in the scheduling queue.
When the processor becomes available, it
dispatches the task from the beginning of the queue
and then executes it until it becomes blocked, inter-
rupted, or until its time-slice expires. It then returns
the task to the end of the queue (i.e., automatically
reschedules it) and dispatches the next ready task.
During these operations, no communication between
the processor and the operating system is necessary
until the running task is complete or an interrupt is
issued.
1.1.10 Synchronization and Communication
The 80960MC also offers instructions to set up and
test semaphores to ensure that concurrent tasks
remain synchronized and no data inconsistency
results. Special data structures, known as communi-
cation ports, provide the means for exchanging
parameters and data structures. Transmission of
PRELIMINARY
information by means of communication ports is
asynchronous and automatically buffered by the
processor.
Communication between tasks by means of ports
can be carried out independently of the operating
system. Once the ports have been set up by the
programmer, the processor handles the message
passing automatically.
1.1.11 High Bandwidth Local Bus
The 80960MC CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus).
The L-Bus provides a direct communication path
between the processor and the memory and I/O
subsystem interfaces. The processor uses the L-Bus
to fetch instructions, manipulate memory and
respond to interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• High bandwidth reads and writes with 66.7
MBytes/s burst (at 25 MHz)
• Special signal to indicate whether a memory trans-
action can be cached
Table 4 defines L-bus signal names and functions;
Table 5 defines other component-support signals
such as interrupt lines.
1.1.12 Multiple Processor Support
One means of increasing the processing power of a
system is to run two or more processors in parallel.
Since microprocessors are not generally designed to
run in tandem with other processors, designing such
a system is usually difficult and costly.
The 80960MC solves this problem by offering a
number of functions to coordinate the actions of
multiple processors. First, messages can be passed
between processors to initiate actions such as
flushing a cache, stopping or starting another
processor, or preempting a task. The messages are
passed on the bus and allow multiple processors to
run together smoothly, with rare need to lock the bus
or memory.
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