80960MC Datasheet, PDF (38/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

80960MC
CLK2
PREVIOUS
CYCLE
INTERRUPT
ACKNOWLEDGEMENT
CYCLE 1
T_X
T_X T_a T_d
T_r
IDLE
(5 BUS STATES)
T_I
T_I
T_I
T_I
INTERRUPT
ACKNOWLEDGEMENT
CYCLE 2
T_I
T_a
T_w
T_d T_r
CLK
INTR
LAD31:0
ALE
ADS
INTA
DT/R
ADDR
ADDR
VECTO R
DEN
LOCK
READY
NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.
Figure 27. Interrupt Acknowledge Transaction
34
PRELIMINARY