80960MC Datasheet, PDF (15/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 3 of 3)
NAME
TYPE
DESCRIPTION
HOLD/
HLDAR
I HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it floats its
three-state bus lines and open-drain control lines, asserts HLDA and enters the T_h
state. When HOLD deasserts, the processor deasserts HLDA and enters the T_i or
T_a state.
HOLD ACKNOWLEDGE RECEIVED: Indicates that the processor has acquired
the bus. When the processor is initialized as the secondary bus master this input is
interpreted as HLDAR.
Refer to Figure 18, HOLD Timing (pg. 22).
HLDA/
HOLDR
O HOLD ACKNOWLEDGE: Relinquishes control of the bus to another bus master.
T.S. When the processor is initialized as the primary bus master this output is
interpreted as HLDA. When HOLD is deasserted, the processor deasserts HLDA
and goes to either the T_i or T_a state.
HOLD REQUEST: Indicates a request to acquire the bus. When the processor is
initialized as the secondary bus master this output is interpreted as HOLDR.
Refer to Figure 18, HOLD Timing (pg. 22).
CACHE/
TAG
O CACHE indicates when an access is cacheable during a T_a cycle. It is not asserted
T.S. during any synchronous access, such as a synchronous load or move instruction
used for sending an IAC message. The CACHE signal floats to a high impedance
state when the processor is idle.
TAG is an input/output signal that, during T_d and T_w cycles, identifies the contents
of a 32-bit word as either data (TAG = 0) or an access descriptor (TAG = 1).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
Table 5. 80960MC Pin Description: Support Signals (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
BADAC
I BAD ACCESS, when asserted in the cycle following the one in which the last
READY of a transaction is asserted, indicates that an unrecoverable error has
occurred on the current bus transaction or that a synchronous load/store instruction
has not been acknowledged.
During system reset the BADAC signal is interpreted differently. When the signal is
high, it indicates that this processor will perform system initialization. When low,
another processor in the system will perform system initialization instead.
RESET
I RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for BADAC and
IAC/INT₀), the three-state output pins are placed in a high impedance state and
other output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The
HIGH to LOW transition of RESET should occur after the rising edge of both CLK2
and the external bus clock and before the next rising edge of CLK2.
Refer to Figure 17, RESET Signal Timing (pg. 21).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
PRELIMINARY
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