80960MC Datasheet, PDF (14/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3)
NAME
TYPE
DESCRIPTION
ADS
W/R
DT/R
O
O.D.
O
O.D.
O
O.D.
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T_a
state and deasserted during the following T_d state. For a burst transaction, ADS is
asserted again every T_d state where READY was asserted in the previous cycle.
WRITE/READ specifies, during a T_a cycle, whether the operation is a write or read.
It is latched on-chip and remains valid during T_d cycles.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the L-Bus. It is low during T_a and T_d cycles for a read or interrupt acknowledgment;
it is high during T_a and T_d cycles for a write. DT/R never changes state when DEN
is asserted.
DEN
O
O.D.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all T_d and T_w states. The DEN# line is an open drain-output of the
80960MC.
READY
LOCK
I
I/O
O.D.
READY indicates that data on LAD lines can be sampled or removed. When
READY is not asserted during a T_d cycle, the T_d cycle is extended to the next cycle
by inserting a wait state (T_w) and ADS is not asserted in the next cycle.
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. When the
pin is already asserted, the processor waits until it is not asserted. When the pin is
not asserted, the processor asserts LOCK during the T_a cycle of the read trans-
action. The processor deasserts LOCK in the T_a cycle of the write transaction.
During the time LOCK is asserted, a bus agent can perform a normal read or write
but not a RMW operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
BE3:0
O
O.D.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
The byte enables are provided in advance of data:
Byte enables asserted during T_a specify the bytes of the first data word.
Byte enables asserted during T_d specify the bytes of the next data word, if any (the
word to be transmitted following the next assertion of READY).
Byte enables that occur during T_d cycles that precede the last assertion of READY
are undefined. Byte enables are latched on-chip and remain constant from one T_d
cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus
agents are required to assert only adjacent byte enables (e.g., asserting just BE0
and BE2 is not permitted) and are required to assert at least one byte enable.
Address bits A₀ and A₁ can be decoded externally from the byte enables.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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PRELIMINARY