80960CF-40 Datasheet, PDF (73/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

A
80960CF-40, -33, -25, -16
PCLK2:1
ADS
! (BLAST
& READY
& !WAIT)
DACKx
(All Modes)
DREQx
(Case 1)
DREQx
(Case 2)
(see Note)
System
Clock
Start DMA
Bus Request
End DMA
Bus Request
high to prevent next bus cycle
t_IS6 t_IH6
high to prevent next bus cycle
DMA
Acknowledge
DMA
Request
t_IS6 t_IH6
Note:
1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized
packing modes and destination synchronized unpacking modes.
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
This applies to all other DMA transfers.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
F_CX018A
accesses (defined by ADS and BLAST).
Figure 44. DREQ and DACK Functional Timing
PCLK2:1
EOP
2 CLKs Min
15 CLKs Max
Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
triggered. EOP must beheld for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
F_CX045A
Figure 45. EOP Functional Timing
PRELIMINARY
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