80960CF-40 Datasheet, PDF (12/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

80960CF-40, -33, -25, -16
A
Name
A31:2
D31:0
BE3:0
W/R
ADS
READY
6
Table 2. 80960CF Pin Description — External Bus Signals (Sheet 1 of 3)
Type
O
S
H(Z)
R(Z)
I/O
S(L)
H(Z)
R(Z)
O
S
H(Z)
R(1)
O
S
H(Z)
R(0)
O
S
H(Z)
R(1)
I
S(L)
H(Z)
R(Z)
Description
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant
bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to
word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word.
During burst accesses, A3:2 increment to indicate successive data cycles.
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configura-
tion. The least significant bit is carried on D0 and the most significant on D31. When the
bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data
bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3 applies to
D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
32-bit bus:
BE3
Byte Enable 3
enable D31:24
BE2
Byte Enable 2
enable D23:16
BE1
Byte Enable 1
enable D15:8
BE0
Byte Enable 0
enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the processor
uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3
Byte High Enable (BHE) enable D15:8
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Byte Low Enable (BLE) enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the processor
uses the BE1 and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3
Not used (driven high or low)
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Address Bit 0 (A0)
WRITE/READ is asserted for read requests and deasserted for write requests. The
W/R signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be valid
in the last cycle of a read access.
ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS
is asserted for the first clock of a bus access.
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. If READY is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY pin is deasserted, wait states continue
to be inserted until READY becomes asserted. This is true for the N_RAD, N_RDD, N_WAD
and N_WDD wait states. The N_XDA wait states cannot be extended.
PRELIMINARY