80960CF-40 Datasheet, PDF (16/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

80960CF-40, -33, -25, -16
A
Table 3. 80960CF Pin Description — Processor Control Signals (Sheet 2 of 2)
Name
CLKIN
CLKMODE
PCLK2:1
V_SS
V_CC
V_CCPLL
NC
Type
I
A(E)
H(Z)
R(Z)
I
A(L)
H(Z)
R(Z)
O
S
H(Q)
R(Q)
–
–
–
–
Description
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
a system as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and
outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.
PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexi-
bility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may also
be connected at the processor to form a single clock signal.
GROUND connections must be connected externally to a V_SS board plane.
POWER connections must be connected externally to a V_CC board plane.
V_CCPLL is a separate V_CC supply pin for the phase lock loop used in 1-x clock mode.
Connecting a simple lowpass filter to V_CCPLL may help reduce clock jitter (T_CP) in
noisy environments. Otherwise, V_CCPLL should be connected to V_CC.
NO CONNECT pins must not be connected in a system.
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PRELIMINARY