80960CF-40 Datasheet, PDF (11/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

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80960CF-40, -33, -25, -16
3.0 PACKAGE INFORMATION
3.1 Package Introduction
This section describes the pins, pinouts and thermal
characteristics for the 80960CF in the 168-pin
Ceramic Pin Grid Array (PGA) package; the
80960CF-33, -25, -16 devices are also available in
the 196-pin Plastic Quad Flat Package (PQFP). For
complete package specifications and information,
see the Packaging Handbook (# 240800).
3.2 Pin Descriptions
This section defines the 80960CF pins. Table 2
presents the legend for interpreting the pin descrip-
tions in the following tables. Pins associated with the
32-bit demultiplexed processor bus are described in
Table 2. Pins associated with the 80960CF DMA
Controller and Interrupt Unit are described in Table 3.
Pins associated with basic processor configuration
and control are described in Table 2.
All pins float while the processor is in the ONCE
mode.
Symbol
Description
I Input only pin
O Output only pin
I/O Pin can be either an input or output
– Pins “must be” connected as described
S(...)
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. Outputs are synchro-
nous to PCLK2:1.
S(E) Edge sensitive input
S(L) Level sensitive input
A(...)
Asynchronous. Inputs may be asynchro-
nous to PCLK2:1.
A(E) Edge sensitive input
A(L) Level sensitive input
H(...)
While the bus is in the Hold Acknowledge
or Bus Backoff state, the pin:
H(1)
H(0)
H(Z)
is driven to V_CC
is driven to V_SS
floats
H(Q) continues to be a valid input
R(...)
While the processor’s RESET pin is low,
the pin:
R(1)
R(0)
R(Z)
is driven to V_CC
is driven to V_SS
floats
R(Q) continues to be a valid output
PRELIMINARY
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