80960CF-40 Datasheet, PDF (53/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

A
80960CF-40, -33, -25, -16
CLKIN
RESET
1.5 V
1.5 V
1.5 V
T_IH T_IS
1.5 V
1.5 V
1.5 V
PCLK2:1
(Case 1)
PCLK2:1
(Case 2)
1.5 V
Max
Min
T_CP
1.5 V
Max
Min
1.5 V
1.5 V
Min
T_CP Max
T_CP
1.5 V
1.5 V
Note: Case 1 and Case 2 show two possible polarities of PCLK2:1
SYNC
Figure 23. Clock Synchronization in the 2-x Clock Mode
F_CX024A
2x CLK
CLKIN
1.5 V
1.5 V
T_IH
T_IS
RESET
1.5 V
Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal
generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising
edge of CLKIN. The RESET pin is sampled when PCLK is high.
F_CX025A
Figure 24. Clock Synchronization in the 1-x Clock Mode
PRELIMINARY
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