80960CF-40 Datasheet, PDF (48/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

80960CF-40, -33, -25, -16
A
900
T_C = 100° C
T_C = 0° C
0
0
I_CC - I_CC under test conditions
f_PCLK (MHz)
33
Figure 18. I_CC vs. Frequency and Temperature—80960CF-33, -25, -16
F_CX020A
1100
T_C
=
T_C = 85° C
I_CC - I_CC under test conditions
0
0
f_PCLK (MHz)
40
Figure 19. I_CC vs. Frequency and Temperature—80960CF-40
F_CX020A
5.0 RESET, BACKOFF AND HOLD
ACKNOWLEDGE
Table 19 lists the condition of each processor output
pin while RESET is asserted (low). Table 20 lists the
condition of each processor output pin while HOLDA
is asserted (high).
In Table 20, with regard to bus output pin state only,
the Hold Acknowledge state takes precedence over
the reset state. Although asserting the RESET pin
internally resets the processor, the processor’s bus
output pins do not enter the reset state if Hold
Acknowledge has been granted to a previous HOLD
request (HOLDA is active). Furthermore, the
processor grants new HOLD requests and enters the
Hold Acknowledge state even while in reset.
42
For example, if HOLD is asserted while HOLDA is
inactive and the processor is in the reset state, the
processor’s bus pins enter the Hold Acknowledge
state and HOLDA is granted. The processor is not
able to perform memory accesses until the HOLD
request is removed, even if the RESET pin is brought
high. This operation is provided to simplify boot-up
synchronization among multiple processors sharing
the same bus.
PRELIMINARY