80960CF-40 Datasheet, PDF (42/77 Pages) Intel Corporation – 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR

80960CF-40, -33, -25, -16
A
Table 18. 80960CF AC Characteristics (16 MHz) (Sheet 3 of 3)
(80960CF-16 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.)
Symbol
Parameter
Min
Max Units Notes
T_IH7
XINT7:0, NMI Input Hold
5
ns (15)
T_IS8
RESET Input Setup (1-x Clock Mode)
3
ns (14)
T_IH8
RESET Input Hold (1-x Clock Mode)
T/4 + 1
ns (14)
NOTES:
1. See Section 4.5.2, AC TIMING WAVEFORMS for waveforms and definitions.
2. See Figure 16 for capacitive derating information for output delays and hold times.
3. See Figure 17 for capacitive derating information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region
Table. WAIT never goes active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or hold times to be
recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the
setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges
to be seen by the processor.
8. These specifications are guaranteed by the processor.
9. These specifications must be met by the system for proper operation of the processor.
10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, DERATING CURVES to
adjust the timing for PCLK2:1 loading.
11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When
the processor is in reset, the input clock may stop even in 1-x mode.
12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ±
0.1% between adjacent cycles.
13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup
and hold times to the falling edge of the CLKIN. (See Figure 23.)
14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.
However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup
and hold times to the rising edge of the CLKIN. (See Figure 24.)
15. The interrupt pins are synchronized internally by the 80960CF. They have no required setup or hold times for proper
operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three con-
secutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge,
the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges.
4.5.1 AC TEST CONDITIONS
The AC Specifications in Section 4.5 are tested with the 50 pF load shown in Figure 7. Figure 16 shows how
timings vary with load capacitance.
Specifications are measured at the 1.5V crossing point, unless otherwise indicated. Input waveforms are
assumed to have a rise and fall time of ≤ 2 ns from 0.8V to 2.0V. See Section 4.5.2, AC TIMING WAVEFORMS
for AC specification definitions, test points and illustrations.
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PRELIMINARY