TDA5250D2 Datasheet, PDF (92/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

confidential
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
Table 5-5 Digital Characteristics with T_A = 25 °C, V_Vdd = 2.1 ... 5.5 V
# Parameter
Sym-
bol
Limit Values
min
typ
max
1 Data rate TX ASK
f_TX.ASK
10
25
2 Data rate TX ASK
f_TX.ASK
10
64
3 Data rate TX FSK
f_TX.FSK
10
40
4 Data rate RX ASK
5 Data rate RX FSK
f_RX.ASK
f_RX.FSK
10
64
10
64
Unit
kBaud
kBaud
kBaud
kBaud
kBaud
Test Conditions
PRBS9,
Manch.@+10dBm
PRBS9,
Manch.@-5dBm
PRBS9,
Manch.@+10dBm
@50kHz dev.
PRBS9, Manch.
PRBS9,
Manch.@100kHz dev.
L Item
I1
I1
I1
I
I
6 Digital Inputs
High-level Input Voltage
Low-level Input Voltage
V_IH
V_dd-0.2
V_IL
0
V_dd
V
0.2
V
7 RXTX Pin 5
TX operation, int. controlled
V_OL
0.4
V
1.15
V
8 CLKDIV Pin 26
t_rise (0.1*Vdd to 0.9*Vdd)
t_fall (0.9*Vdd to 0.1*Vdd)
Output High Voltage
Output Low Voltage
t_r
t_f
V_OH
V_OL
35
ns
30
ns
Vdd-0.4
V
0.4
V
Bus Interface Characteristics
I
@Vdd=3V
I
Isink=800uA
Isink=3mA
@Vdd=3V
I
load 10pF
load 10pF
Isorce=350uA
Isink=400uA
9 Pulse width of spikes which
t_SP
0
must be suppressed by the
input filter
10 LOW level output voltage at
V_OL
BusData
11 SLC clock frequency
f_SLC
0
12 Bus free time between
t_BUF
1.3
STOP and START condition
13 Hold time (repeated) START t_HO.STA 0.6
condition.
14 LOW period of BusCLK
clock
15 HIGH period of BusCLK
clock
16 Setup time for a repeated
START condition
t_LOW
1.3
t_HIGH
0.6
t_SU.STA
0.6
50
ns
V_dd=5V
I
0.4
V
3mA sink current I
V_dd=5V
400 kHz
V_dd=5V
I
µs
only I²C mode
I
V_dd=5V
µs
After this period, the first I
clock pulse is generated,
only I²C
µs
V_dd=5V
I
µs
V_dd=5V
I
µs
only I²C mode
I
Wireless Components
5-7
Specification, July 2002