TDA5250D2 Datasheet, PDF (32/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

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TDA 5250 D2
preliminary
Functional Description
If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is
applied at PwdDD after each data valid decision.
In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH
the CLK output is on during ON time and off during OFF time. If D9=1, the CLK
output is always on.
TIMER MODE: Only the internal Timer (determined by the ON_TIME and
OFF_TIME registers) is active to support an external logic with periodical
Interrupts. After ON_TIME + OFF_TIME a 15µs LOW impulse is applied at the
PwdDD pin (Pin 27).
Action
PwdDD pin in
TIMER MODE
ON_TIME
Register 04H
OFF_TIME
Register 05H
ON_TIME
Register 04H
15µs
15µs
Figure 3-11 Timing for Timer Mode
t
t
timing_timermode.wmf
Wireless Components
3 - 22
Specification, July 2002