TDA5250D2 Datasheet, PDF (72/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

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TDA 5250 D2
preliminary
Applications
4.7 Data Valid Detection
In order to detect valid data two criteria must be fulfilled.
One criteria is the data rate, which can be set in register 06h and 07h. The other
one is the received RF power level, which can be set in register 08h in form of
the RSSI threshold voltage. Thus for using the data valid detection FSK
modulation is recommended.
Timing for data detection looks like the following. Two settings are possible:
„Continuous“ and „Single Shot“, which can be set by D5 and D6 in register 00H.
Data
Sequenzer enables
data detection
Counter Reset
reset
Gate time
Compare with single
TH and latch result
Compare with double
TH and latch result
(Frequency) Window
Count Complete
start of conversion
reset
count
comp.
comp.
ready*
possible start of next conversion
t
t
t
count
t
comp.
t
t
t
Figure 4-31 Frequency Detection timing in continuous mode
Frequ_Detect_Timing_continuous.wmf
Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to
HIGH transition about 2.6ms after RX is activated (see Figure 3-15).
Note 2: The positive edge of the „Window Count Complete“ signal latches the
result of comparison of the analog to digital converted RSSI voltage with TH3
(register 08H). A logic combination of this output and the result of the
comparison with single/double TH_x defines the internal signal „data_valid“.
Figure 4-31 shows that the logic is ready for the next conversion after 3 periods
of the data signal.
Wireless Components
4 - 32
Specification, July 2002