TDA5250D2 Datasheet, PDF (21/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

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TDA 5250 D2
preliminary
Functional Description
3.4.9 Data Filter
The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-
chip. The bandwidth can be adjusted between approximately 5kHz and 102kHz
via the bits D4 to D7 of the LPF register as shown in Table 4-10.
ASK / FSK
INTERNAL BUS
Figure 3-5 Data Filter architecture
OTA
data_filter.wmf
3.4.10 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100kHz. The self-
adjusting threshold is generated by a RC-network (LPF) or by use of one or both
peak detectors depending on the baseband coding scheme as described in
Section 4.6. This can be controlled by the D15 bit of the CONFIG register as
shown in the following table.
Table 3-4 Sub Address 00H: CONFIG
Bit Function
Description
D15 SLICER
0= Lowpass Filter, 1= Peak Detector
Default
0
3.4.11 Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages
in a fast-attack and slow-release manner that are proportional to the positive
and negative peak voltages appearing in the data signal. These voltages may
be used to generate a threshold voltage for non-Manchester encoded signals,
for example. The time-constant of the fast-attack/slow-release action is
determined by external RC networks.
Wireless Components
3 - 11
Specification, July 2002