TDA5250D2 Datasheet, PDF (24/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

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TDA 5250 D2
preliminary
Functional Description
3.4.15 Bus Interface and Register Definition
The TDA5250 supports the I²C bus protocol (2 wire) and a 3-wire bus protocol.
Operation is selectable by the BusMode pin (pin 2) as shown in the following
table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered
input stage. The BusData pin is bidirectional where the output is open drain
driven.
Table 3-6 Bus Interface Format
Function
I²C Mode
3-wire Mode
BusMode
Low
High
EN
High= inactive,
Low= active
BusCLK
Clock input
BusData
Data in/out
BusData
16
BusCLK
17
EN
24
BusMode
2
I²C / 3-wire INTERNAL BUS
INTERFACE
11100000
CHIP ADDRESS
Figure 3-7 Bus Interface
i2c_3w_bus.wmf
Note: The Interface is able to access the internal registers at any time, even in
POWER DOWN mode. There is no internal clock necessary for Interface
operation.
I²C Bus Mode
In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.
Data Transition:
Data transition on the pin BusData can only occur when BusCLK is LOW.
BusData transitions while BusCLK is HIGH will be interpreted as start or stop
condition.
Wireless Components
3 - 14
Specification, July 2002