TDA5250D2 Datasheet, PDF (23/97 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

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TDA 5250 D2
preliminary
Functional Description
3.4.14 Timing and Data Control Unit
The timing and data control unit contains a wake-up logic unit, an I²C/3-wire
microcontroller interface, a “data valid” detection unit and a set of configuration
registers as shown in the subsequent figure.
I²C / 3Wire
INTERFACE
INTERNAL BUS
18 MHz
XTAL-Osz.
RSSI ^{6 Bit}
ADC
RX DATA
DATA VALID
DETECTOR
AM PLITUDE
threshold TH3
FREQUENCY
window
TH1<T_GATE<TH2
WAKEUP
LOGIC
32kHz
RC-Osz.
FSK DATA
ASK DATA
BLOCK ENABLE
ASK / FSK
RX / TX
CONTROL
LOGIC
POWER ON
SEQUENCER
Figure 3-6 Timing and Data Control Unit
CLKDiv
PwdDD
Data
AskFsk
RxTx
Reset
logic.wmf
The I²C / 3-wire Bus Interface gives an external microcontroller full control over
important system parameters at any time.
It is possible to set the device in three different modes: Slave Mode, Self Polling
Mode and Timer Mode. This is done by a state machine which is implemented
in the WAKEUP LOGIC unit. A detailed description is given in Section 3.4.16.
The DATA VALID DETECTOR contains a frequency window counter and an
RSSI threshold comparator. The window counter uses the incoming data signal
from the data slicer as the gating signal and the crystal oscillator frequency as
the timebase to determine the actual datarate. The result is compared with the
expected datarate.
The threshold comparator compares the actual RSSI level with the expected
RSSI level.
If both conditions are true the PwdDD pin is set to LOW in self polling mode as
you can see in Section 3.4.1.6. This signal can be used as an interrupt for an
external µP. Because the PwdDD pin is bidirectional and open drain driven by
an internal pull-up resistor it is possible to apply an external LOW thus enabling
the device.
Wireless Components
3 - 13
Specification, July 2002