HYS64T32000GU Datasheet, PDF (9/67 Pages) Infineon Technologies AG – 240-Pin Unbuffered DDR2 SDRAM Modules

HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
1.3
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1 for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
Table 5 Pin Configuration of UDIMM
Pin#
Name Pin Buffer Function
Type Type
Clock Signals
185
CK0 I
SSTL Clock Signals 2:0
137
CK1 I
SSTL
220
CK2 I
SSTL
186
CK0 I
SSTL Complement Clock Signals 2:0
138
CK1 I
SSTL
221
CK2 I
SSTL
52
CKE0 I
SSTL Clock Enable Rank 0
171
CKE1 I
SSTL Clock Enable Rank 1
Note: 2 Ranks module
NC NC —
Note: 1 Rank module
Control Signals
193
S0
I
SSTL Chip Select Rank 0
76
S1
I
SSTL Chip Select Rank 1
Note: 2 Ranks module
NC NC —
Note: 1 Rank module
192
RAS I
SSTL Row Address Strobe
74
CAS I
SSTL Column Address Strobe
73
WE I
SSTL Write Enable
Address Signals
71
BA0 I
SSTL Bank Address Bus 1:0
190
BA1 I
SSTL
54
BA2 I
SSTL Bank Address Bus 2
Note: greater than 512Mb DDR2 SDRAMS
NC NC —
Note: less than 1Gb DDR2 SDRAMS
188
A0
I
SSTL Address Bus 12:0
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
Data Sheet
9
Rev. 0.87, 2004-06
09122003-GZEK-H4J6