HYS64T32000GU Datasheet, PDF (28/67 Pages) Infineon Technologies AG – 240-Pin Unbuffered DDR2 SDRAM Modules

HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
5.1
AC Timing Parameter by Speed Grade (Component level data, for reference only)
Table 21 AC Timing - Absolute Specifications –5 / –3.7
Symbol Parameter
–5
DDR2–400
min.
max.
t_AC
DQ output access time from CK/CK
t_CCD
CAS A to CAS B Command Period
t_CH
CK, CK high-level width
t_CK
Clock cycle time
− 600
2
0.45
5000
5000
+ 600
-
0.55
8000
8000
t_CKE
t_CL
t_DAL
t_DELAY
t_DH
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSS
CKE minimum high and low pulse width
3
-
CK, CK low-level width
0.45
0.55
Auto precharge write recovery + precharge time WR+t_RP -
Minimum time clocks remain ON after CKE
asynchronously drops low
t_IS+t_CK+t_I -
H
DQ and DM input hold time
400
-
DQ and DM input pulse width (each input)
0.35
-
DQS output access time from CK/CK
− 500 + 500
DQS input low (high) pulse width (write cycle) 0.35
-
Write command to 1st DQS latching transition WL -
0.25
WL
+0.25
t_DQSQ
DQS-DQ skew
(for DQS & associated DQ signals)
-
350
t_DS
DQ and DM input setup time
t_DSH
DQS falling edge hold time from CLK
(write cycle)
400
-
0.2
-
t_DSS
DQS falling edge to CLK setup time
(write cycle)
0.2
-
t_HP
t_HZ
t_IH
t_IPW
t_IS
t_LZ(DQ)
t_LZ(DQS)
t_MRD
t_OIT
t_RAS
t_RC
t_RCD
Clock Half Period
Data-out high-impedance time from CK/CK
Address and control input hold time
min. (t_CL, t_CH)
-
t_ACmax
600
-
Control and Addr. input pulse width (each input) 0.6
-
Address and control input setup time
600
-
DQ low-impedance from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
2*t_ACmin
t_ACmin
2
t_ACmax
t_ACmax
-
OCD drive mode output delay
0
12
Active to Precharge command
40
70000
Active to Active/Auto-refresh command period 55
-
Active to Read or Write delay (with and without 15
-
Auto-Precharge) delay
–3.7
DDR2–533
min. max.
-500 +500
2
-
0.45 0.55
5000 8000
3750 8000
3
-
0.45 0.55
WR+t_RP -
t_IS+t_CK -
+t_IH
350
-
0.35 -
−450 +450
0.35 -
WL
-0.25
WL
+0.25
-
300
350
-
0.2
-
0.2
-
min. (t_CL, t_CH)
-
t_ACmax
600
-
0.6
-
600
-
2*t_ACmin
t_ACmin
2
t_ACmax
t_ACmax
-
0
12
45
70000
60
-
15
-
Unit Notes
ps ¹⁾
t_CK ¹⁾
t_CK ¹⁾
ps ¹⁾²⁾
ps ¹⁾³⁾
t_CK ¹⁾
t_CK ¹⁾
t_CK ¹⁾
ns ¹⁾
ps ¹⁾⁴⁾
t_CK ¹⁾
ps ¹⁾
t_CK ¹⁾
t_CK ¹⁾
ps ¹⁾
ps ¹⁾⁴⁾
t_CK ¹⁾
t_CK ¹⁾
1)
ps ¹⁾
ps ¹⁾⁴⁾
t_CK ¹⁾
ps ¹⁾⁴⁾
ps ¹⁾
ps ¹⁾
t_CK ¹⁾
ns ¹⁾
ns ¹⁾
ns ¹⁾
ns ¹⁾
Data Sheet
28
Rev. 0.87, 2004-06
09122003-GZEK-H4J6