HYS64T32000GU Datasheet, PDF (23/67 Pages) Infineon Technologies AG – 240-Pin Unbuffered DDR2 SDRAM Modules

HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 13 Absolute Maximum Ratings
Parameter
Voltage on any pins relative to V_SS
Voltage on V_DD relative to V_SS
Voltage on V_{DD Q} relative to V_SS
Storage temperature range
Storage Humidity (without condensation)
Symbol
V_IN, V_OUT
V_DD
V_DDQ
T_HSTG
H_STG
Limit Values
min.
max.
– 0.5
2.3
– 1.0
2.3
– 0.5
2.3
-55
+100
5
95
Unit
V
V
°C
%
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Table 14 Operating Conditions
Parameter
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Barometric Pressure (operating & storage)
Symbol
T_OPR
T_CASE
PBar
Limit Values
min.
max.
0
+55
0
+95
+69
+105
Unit Notes
°C
°C
kPa
1)2)3)4)
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the
DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2.
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to t_REFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the
DRAM is below 85°C case temperature before initiating self-refresh operation.
Table 15 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol Limit Values
Unit Notes
min.
nom.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
DC Input Logic Low
In / Output Leakage Current
V_DD
V_DDQ
V_REF
V_DDSPD
V_{IH (DC)}
V_{IL (DC)}
I_L
1.7
1.7
0.49 x V_DDQ
1.7
V_REF + 0.125
– 0.30
–5
1.8
1.8
0.5 x V_DDQ
–
–
–
1.9
V
-
1.9
V
1)
0.51 x V_DDQ V
2)
3.6
V
V_DDQ + 0.3
V
V_REF – 0.125 V
5
µA
3)
1) Under all conditions, V_DDQ must be less than or equal to V_DD
2) Peak to peak AC noise on V_REF may not exceed ± 2% V_REF (DC).V_REF is also expected to track noise variations
in V_DDQ.
3) Voltage for pin connector under test input of 0 V ≤ V_IN ≤ V_DDQ + 0.3 V; all othe pins at 0 V. Current is per pin
Data Sheet
23
Rev. 0.87, 2004-06
09122003-GZEK-H4J6