HYS64T32000GU Datasheet, PDF (56/67 Pages) Infineon Technologies AG – 240-Pin Unbuffered DDR2 SDRAM Modules

HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Table 29 SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte# Description
35
t_DH.min [ns]
36
t_WR.min [ns]
37
t_WTR.min [ns]
38
t_RTP.min [ns]
39
Analysis Characteristics
40
t_RC and t_RFC Extension
41
t_RC.min [ns]
42
t_RFC.min [ns]
43
t_CK.max [ns]
44
t_DQSQ.max [ns]
45
t_QHS.max [ns]
46
PLL Relock Time
47
T_CASE.max Delta / ∆ T_4R4W Delta
48
Psi(T-A) DRAM
49
∆T₀ (DT0)
50
∆T_2N (DT2N, UDIMM) or ∆T_{2Q (} (DT2Q, RDIMM)
51
∆T_2P (DT2P)
52
∆T_3N (DT3N)
53
∆T_3P.fast (DT3P fast)
54
∆T_3P.slow (DT3P slow)
55
∆T_4R (DT4R) / ∆T_{4R4W S} Sign (DT4R4W)
56
∆T_5B (DT5B)
57
∆T₇ (DT7)
58
Psi(ca) PLL
59
Psi(ca) REG
60
∆T_PLL (DTPLL)
61
∆T_REG (DTREG) / Toggle Rate
62
SPD Revision
63
Checksum of Bytes 0-62
Data Sheet
56
256 MB
512 MB
×64
×64
1 Rank (×16) 1 Rank (×8)
PC2–3200U–333
Rev. 1.1
Rev. 1.1
HEX
HEX
27
27
3C
3C
28
28
1E
1E
00
00
00
00
3C
3C
69
69
80
80
23
23
2D
2D
00
00
51
51
72
78
42
32
23
24
1D
1E
19
1B
1C
1E
16
17
2E
28
1A
1B
2D
1E
00
00
00
00
00
00
00
00
11
11
0B
23
512 MB
×72
1 Rank (×8)
Rev. 1.1
HEX
27
3C
28
1E
00
00
3C
69
80
23
2D
00
51
78
32
24
1E
1B
1E
17
28
1B
1E
00
00
00
00
11
35
Rev. 0.87, 2004-06
09122003-GZEK-H4J6