HYB39S256400DT Datasheet, PDF (9/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pin
DQM
LDQM
UDQM
V_DD
V_SS
V_DDQ
V_SSQ
Type Signal Polarity Function
Input Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
Supply –
–
Power and ground for the input buffers and the core logic.
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
INFINEON Technologies
9
2002-04-23