HYB39S256400DT Datasheet, PDF (17/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operating Currents
T_A = 0 to 70 ^oC; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V
Parameter & Test Condition
Symb. -6 -7 -7.5 -8
Note
max.
Operating Current
t_RC = t_RC(min),
IDD1 100 80
80
80 mA 3, 4
One bank active, Burst length = 1
Io = 0 mA
Precharge Standby Current
in Power Down Mode
CS =VIH (min.), IDD2P 2
2
2
2 mA 3
CKE<=Vil(max)
Precharge Standby Current
in Non-Power Down Mode
CS = VIH (min.), IDD2N 35
30
30
25 mA 3
CKE>=Vih(min)
No Operating Current
CS = VIH(min), IDD3N 40
35
35
30 mA 3
CKE>=VIH(min.)
active state ( max. 4 banks)
CS = VIH(min), IDD3P 5
5
5
5 mA 3
CKE<=VIL(max.)
Burst Operating Current
Read command cycling
IDD4 110 90 90 70 mA 3, 4
Auto Refresh Current
Auto Refresh command cycling
t_RFC= t_RFC(min)
t_RFC= 7.8 µs
220 190 190 160 mA
IDD5
3
3
3
3 mA ⁵
Self Refresh Current
(standard components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x4, x8 IDD6
3
3
3
3 mA
x16
1.5 1.5 1.5 1.5 mA
Self Refresh Current
(low power components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x8, x16 IDD6 0.85 0.85 0.85 0.85 mA
Notes:
3. These parameters depend on the cycle rate. All values are measured at 166 MHz for “-6”, at 133 MHz for
“-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once
during tck.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
5. t_RFC= t_RFC(min) “burst refresh”, t_RFC= 7.8 µs “distributed refresh”.
INFINEON Technologies
17
2002-04-23