HYB39S256400DT Datasheet, PDF (19/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Parameter
Row Cycle Time during Auto
Refresh
Activate(a) to Activate(b)
Command period
CAS(a) to CAS(b) Command
period
Symbol
Limit Values
Unit
-6
PC166-
333
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max. min. max.
t_RFC 60
63
67
70
ns
t_RRD 12 – 14 – 15 – 16 – ns 5
t_CCD
1
–
1
–
1
–
1
– CLK
Refresh Cycle
Refresh Period (8192 cycles) t_REF – 64 – 64 – 64 – 64 ms
Self Refresh Exit Time
t_SREX
1
–
1
–
1
–
1
CLK
Read Cycle
Data Out Hold Time
t_OH 2.5 – 3 – 3 – 3 – ns 2,
6
Data Out to Low Impedance Time
t_LZ
0
–
0
–
0
–
0
– ns
Data Out to High Impedance Time
t_HZ
3
6
3
7
3
7
3
8 ns
DQM Data Out Disable Latency
t_DQZ
–
2
–
2
–
2
–
2 CLK
Write Cycle
Last Data Input to Precharge
(Write without AutoPrecharge)
t_WR 12 – 14 – 15 – 15 – ns 7
Last Data Input to Activate
(Write with AutoPrecharge)
t_DAL,min
(twr/tck) + (trp/tck)
CLK 8
DQM Write Mask Latency
t_DQW
0
–
0
–
0
–
0
– CLK
INFINEON Technologies
19
2002-04-23