HYB39S256400DT Datasheet, PDF (8/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity Function
CLK
Input Pulse Positive The system clock input. All of the SDRAM inputs are
Edge sampled on the rising edge of the clock.
CKE
Input
Level Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input Pulse Active CS enables the command decoder when low and disables
Low
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input Pulse Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A12 Input Level –
During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
BA0, BA1 Input Level –
DQx
Input Level –
Output
In addition to the column address, A10(= AP) is used to
invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
INFINEON Technologies
8
2002-04-23