HYB39S256400DT Datasheet, PDF (6/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Column Address
Counter
Column Addresses
A0 - A9, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 1
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 2
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 3
8192
x 1024
x 8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)
Control Logic &
Timing Generator
SPB04128
INFINEON Technologies
6
2002-04-23