HYB39S256400DT Datasheet, PDF (10/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Device
State
Idle³
CKE CKE DQM BA0 AP= Addr CS RAS CAS WE
n-1 n
BA1 A10 .
H
X
X
V
V
V
L
L
HH
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active³
H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge Active³
H
X
X
V
H
V
L
H
L
L
Read
Active³
H
X
X
V
L
V
L
H
L
H
Read with Autoprecharge Active³
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
HH
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self
Refr.)
H
X
X
X
L
H
X
X
X
X
L
H
H
X
Clock Suspend Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Idle
H
X
X
X
H
L
X
X
X
X
Active⁴
L
H
H
H
Clock Suspend Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Exit
Any
H
X
X
X
(Power
L
H
X
X
X
X
Down)
L
H
H
L
Data Write/Output Enable Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable Active
H
X
H
X
X
X
X
X
X
X
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle
device is in clock suspend mode.
INFINEON Technologies
10
2002-04-23