HYB39S256400DT Datasheet, PDF (7/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Column Address
Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing)
Control Logic &
Timing Generator
SPB04129
INFINEON Technologies
7
2002-04-23