HYB39S256400DT Datasheet, PDF (18/22 Pages) Infineon Technologies AG – 256 MBit Synchronous DRAM

HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
AC Characteristics 1)2)
T_A = 0 to 70 ^oC; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit
-6
PC166-
333
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3 t_CK
CAS Latency = 2
Clock Frequency
CAS Latency = 3 t_CK
CAS Latency = 2
Access Time from Clock
CAS Latency = 3 t_AC
CAS Latency = 2
Clock High Pulse Width
t_CH
Clock Low Pulse Width
t_CL
Transition time
t_T
6 – 7 – 7.5 – 8 – ns
7.5 – 7.5 – 10 – 10 – ns
– 166 – 143 – 133 – 125 MHz
– 133 – 133 – 100 – 100 MHz
– 5 – 5.4 – 5.4 –
– 5.4 – 5.4 – 6 –
6 ns 2,
6 ns ^3,
6
2 – 2.5 – 2.5 – 3 – ns
2 – 2.5 – 2.5 – 3 – ns
0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns
Setup and Hold Times
Input Setup Time
t_IS 1.5 – 1.5 – 1.5 – 2
Input Hold Time
t_IH 0.8 – 0.8 – 0.8 – 1
CKE Setup Time
t_CKS 1.5 – 1.5 – 1.5 – 2
CKE Hold Time
t_CKH 0.8 – 0.8 – 0.8 – 1
Mode Register Set-up to Active t_RSC 2 – 2 – 2 – 2
delay
Power Down Mode Entry Time t_SB 0 6 0 7 0 7.5 0
– ns 4
– ns 4
– ns 4
– ns 4
– CLK
8 ns
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
t_RCD 15 – 15 – 20 – 20 – ns 5
t_RP 15 – 15 – 20 – 20 – ns 5
t_RAS 36 100k 37 100k 45 100k 48 100k ns 5
t_RC 60 – 60 – 67 – 70 – ns 5
INFINEON Technologies
18
2002-04-23