HYS72D32500GR Datasheet, PDF (8/39 Pages) Infineon Technologies AG – Registered DDR SDRAM-Modules

2
Pin Configuration
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
Table 3 Pin Definitions and Functions
Symbol
Type
A0 – A11, A12
Input
BA0, BA1
Input
DQ0 – DQ63
Input/Output
CB0 – CB7
Input/Output
RAS
Input
CAS
Input
WE
Input
CKE0, CKE1
Input
DQS0 – DQS8
Input/Output
CK0, CK0
Input
DM0 – DM8
Input
DQS9 – DQS17
Input/Output
CS0, CS1
Input
V_DD
V_SS
V_DDQ
V_DDID
V_DDSPD
V_REF
SCL
Supply
Supply
Supply
Output
Supply
Supply
Input
SDA
Output
SA0 – SA2
Input
NC
Input
DU
Input
RESET
Input
Function
Address Inputs (A12 for 256 MB & 512 MB based modules)
Bank Selects
Data Input/Output
Check Bits (×72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
SDRAM low data strobes
Differential Clock Input
SDRAM low data mask
high data strobes
Chip Selects
Power (+2.5 V)
Ground
I/O Driver power supply
V_DD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Serial bus data line
slave address select
no connect
don’t use
Reset pin (forces register inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the
end of this datasheet
Data Sheet
8
Rev. 1.03 2004-01