HYS72D32500GR Datasheet, PDF (14/39 Pages) Infineon Technologies AG – Registered DDR SDRAM-Modules

HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6 Absolute Maximum Ratings
Parameter
Symbol Values
Unit
min.
max.
Input/Output voltage relative to V_SS
V_IN, V_OUT
–0.5
3.6
V
Power supply voltage on V_DD/V_DDQ to V_SS
Storage temperature range
V_DD, V_DDQ
T_STG
–0.5
–55
3.6
V
+150
o_C
Power dissipation (per SDRAM component)
P_D
–
1
W
Data out current (short circuit)
I_OS
–
50
mA
Attention: Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional
operation should be restricted to recommended operation conditions. Exposure to higher than
recommended voltage for extended periods of time affect device reliability
Table 7 Supply Voltage Levels
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
Termination Voltage
EEPROM supply voltage
Symbol
V_DD
V_DDQ
V_REF
V_TT
V_DDSPD
Values
min.
2.3
2.3
0.49 × V_DDQ
V_REF – 0.04
2.3
nom.
2.5
2.5
0.5 × V_DDQ
V_REF
2.5
max.
2.7
2.7
0.51 × V_DDQ
V_REF + 0.04
3.6
Unit/
Notes
V
V 1)
V 2)
V 3)
V
Note:
1. Under all conditions, V_DDQ must be less than or equal to V_DD
2. Peak to peak AC noise on V_REF may not exceed ± 2% V_{REF (DC)}.
V_REF is also expected to track noise variations in V_DDQ.
3. V_TT of the transmitting device must track V_REF of the receiving device
.
Table 8 DC Operating Conditions (SSTL_2 Inputs)
(V_DDQ = 2.5 V, T_A = 70 °C, Voltage Referenced to V_SS)
Parameter
Symbol
Values
min.
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
V_{IH, (DC)}
V_{IL, (DC)}
I_IL
I_OL
V_REF +0.15
–0.30
–5
–5
Note:
max.
V_DDQ +0.3
V_REF –0.15
5
5
Unit/
Notes
V 1)
V
µA 1)
µA 2)
1. The relationship between the V_DDQ of the driving device and the V_REF of the receiving device is what determines
noise margins. However, in the case of V_{IH (max.)} (input overdrive), it is the V_DDQ of the receiving device that is
referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2
outputs (such as a translator), and therefore no V_DDQ supply voltage connection, inputs must tolerate input
overdrive to 3.0 V (High corner V_DDQ + 300 mV).
2. For any pin under test input of 0 V ≤ V_IN ≤ V_DDQ + 0.3 V. Values are shown per DDR-SDRAM component
Data Sheet
14
Rev. 1.03 2004-01