HYS72D32500GR Datasheet, PDF (25/39 Pages) Infineon Technologies AG – Registered DDR SDRAM-Modules

HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
Table 14 SPD Codes for HYS72D64500GR–[7F/7/8]–B
Label Code
Byte#
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Jedec SPD Revision
Description
Data Width (LSB)
Data Width (MSB)
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
Module Density per Rank
tAS, tCS [ns]
Data Sheet
25
×72
1 rank
reg
PC2100R –
20220
Rev. 0.0
HEX
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C0
75
75
00
00
3C
3C
3C
2D
80
90
×72
1 rank
reg
PC2100R –
20330
Rev. 0.0
HEX
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C0
75
75
00
00
50
3C
50
2D
80
90
×72
1 rank
reg
PC1600R –
20220
Rev. 0.0
HEX
48
00
04
80
80
02
82
04
04
01
0E
04
0C
01
02
26
C0
A0
80
00
00
50
3C
50
32
80
B0
Rev. 1.03 2004-01