HYS72D32500GR Datasheet, PDF (19/39 Pages) Infineon Technologies AG – Registered DDR SDRAM-Modules

HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
Table 12 AC Timing - Absolute Specifications –8/–7/-7F
Parameter
Symbol
–8
–7
DDR200
DDR266A
Min. Max. Min. Max.
Address and control input setup t_IS
time
1.1 —
0.9 —
1.1 —
1.0 —
–7F
DDR266F
Min. Max.
0.9 —
1.0 —
Unit Note/
Test
Condition ¹⁾
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Address and control input hold t_IH
time
1.1 —
1.1 —
0.9 —
1.0 —
0.9 —
1.0 —
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
Active to Precharge command
Active to Active/Auto-refresh
command period
t_RPRE
t_RPRES
t_RPST
t_RAS
t_RC
Auto-refresh to Active/Auto-
t_RFC
refresh command period
Active to Read or Write delay t_RCD
Precharge command period t_RP
Active to Autoprecharge delay t_RAP
Active bank A to Active bank B t_RRD
command
Write recovery time
t_WR
Auto precharge write recovery + t_DAL
precharge time
Internal write to read command t_WTR
delay
Exit self-refresh to non-read
command
t_XSNR
Exit self-refresh to read
command
t_XSRD
Average Periodic Refresh
t_REFI
Interval
0.9 1.1
0.9
1.5 —
NA
0.40 0.60 0.40
50 120E+3 45
70 —
65
1.1
0.9 1.1
t_CK
NA —
t_CK
0.60 0.40 0.60 ns
120E+3 45
—
65
120E+3 t_CK
—
ns
80 —
75 —
75 —
ns
20 —
20 —
20 —
ns
20 —
20 —
20 —
ns
20 —
20 —
20 —
ns
15 —
15 —
15 —
ns
15 —
15 —
15 —
ns
(t_wr/t_CK) + (t_rp/t_CK)
t_CK
1—
1
—
1—
t_CK
80 —
75 —
75 —
ns
200 —
200 —
200 —
t_CK
— 7.8
— 7.8
— 7.8
µs
CL > 1.5 ^2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
CL > 1.5 ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266a, DDR266F and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
19
Rev. 1.03 2004-01