HYS64D16301HU-5-C Datasheet, PDF (7/35 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Overview
Table 2 Ordering Information
Type
PC3200 (CL=3)
HYS64D16301HU-5-C
HYS64D32300HU-5-C
HYS72D32300HU-5-C
HYS64D64320HU-5-C
HYS72D64320HU-5-C
Compliance Code Description
SDRAM Technology
PC3200U-30330-C0
PC3200U-30330-A0
PC3200U-30330-A0
PC3200U-30330-B0
PC3200U-30330-B0
one rank 128MB DIMM
256 Mbit (× 16)
one rank 256MB DIMM
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM
256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC2700 (CL=2.5)
HYS64D16301HU-6-C
HYS64D32300HU-6-C
HYS72D32300HU-6-C
HYS64D64320HU-6-C
HYS72D64320HU-6-C
PC2700U-25330-C0
PC2700U-25330-A0
PC2700U-25330-A0
PC2700U-25330-B0
PC2700U-25330-B0
one rank 128MB DIMM
256 Mbit (× 16)
one rank 256MB DIMM
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM
256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD¹⁾ latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.0, 2003-07