HYS64D16301HU-5-C Datasheet, PDF (10/35 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4 Pin Configuration (cont’d)
Frontside
PIN# Symbol
PIN# Symbol
40
DQ27
41
A2
85
V_DD
86
DQS7
42
V_SS
43
A1
87
DQ58
88
DQ59
44
NC / CB0
45
NC / CB1
89
V_SS
90
NC
46
V_DD
47
NC / DQS8
91
SDA
92
SCL
Backside
PIN# Symbol
132
V_SS
133 DQ31
134 NC / CB4
135 NC / CB5
136
V_DDQ
137 CK0
138
CK0
139
V_SS
PIN#
177
178
179
180
181
182
183
184
Symbol
DM7/DQS16
DQ62
DQ63
V_DDQ
SA0
SA1
SA2
V_DDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on × 64 organised non-ECC
modules.
Table 5
Density
128 MB
256 MB
256 MB
512 MB
512 MB
Address Format
Organization Memory SDRAMs # of
# of row/bank/
Ranks
SDRAMs columns bits
16M × 64 1
16M × 1 4
6
13 / 2 / 10
32M × 64 1
32M × 8 8
13 / 2 / 11
32M × 72 1
32M × 8 9
13 / 2 / 11
64M × 64 2
32M × 8 16
13 / 2 / 11
64M × 72 2
32M × 8 18
13 / 2 / 11
Refresh Period Interval
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
Data Sheet
10
V1.0, 2003-07