HYS64D16301HU-5-C Datasheet, PDF (6/35 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

184-Pin Unbuffered Dual-In-Line Memory Modules
Reg DIMM
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
HYS64D16x01HU-[5/6]-C
1
Overview
1.1
Features
• 184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory
applications
• One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
• Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E²PROM
• JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
• Jedec standard reference layout
• Gold plated contacts
• DDR400 Speed Grade supported
• Lead-free
Table 1 Performance
Part Number Speed Code
Module Speed Grade
Component Module
max. Clock Frequency
@ CL = 3
@ CL = 2.5
@ CL = 2
f_CK3
f_CK2.5
f_CK2
–5
DDR400B
PC3200-3033
200
166
133
–6
DDR333B
PC2700-2533
166
166
133
Unit
–
–
MHz
MHz
MHz
1.2
Description
The HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, and HYS64D16x01HU-[5/6]-C are industry
standard 184-Pin Unbuffered Dual-In-Line Memory Modules (Reg DIMM) organized as 16M × 64, 32M × 64 and
64M × 64 for non-parity and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is
designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted
on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E²PROM device
using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes
are available to the customer
Data Sheet
6
V1.0, 2003-07