HYS64T32000GDL Datasheet, PDF (6/48 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Module

200-Pin Small Outline Dual-In-Line Memory Module
DDR2 SDRAM
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
1
Overview
This chapter gives an overview of the 1.8 V 200-Pin Small Outline Dual-In-Line Memory Module, 256 MByte and
512 MByte and describes its main characteristics.
1.1
Features
• 200-pin Non-ECC Unbuffered 8-Byte Dual-In-Line
DDR2 SDRAM Module for Notebooks and other
application where small form factors are required.
• One rank 32M × 64, two ranks 64M × 64 and
128M × 64 module organisation and 32M × 16 and
64M × 8 chip organisation
• JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
• 256 ,512 MByte and 1GByte modules built with
512Mb DDR2 SDRAMs in 60-ball FBGA
(P–TFBGA–60) and 84-ball FBGA (P–TFBGA–84)
chipsize packages
• Programmable CAS Latencies (3, 4 and 5), Burst
Length (4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment(OCD) and
On-Die Termination(ODT)
• Serial Presence Detect with E²PROM
• Low Profile Modules form factor: 67.60 mm x 30.00
mm (MO-224)
• Based on JEDEC standard reference layouts Raw
Card “A”, “C” and “D”
Table 1 Performance
Product Type Speed Code
Speed Grade
max. Clock Frequency
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
@CL5
@CL4
@CL3
–3.7
PC2–4200 4–4–4
f_CK5 266
f_CK4 266
f_CK3 200
t_RCD 15
t_RP 15
t_RAS 45
t_RC 60
–5
PC2–3200 3–3–3
200
200
200
15
15
40
55
Units
—
MHz
MHz
MHz
ns
ns
ns
ns
1.2
Description
The INFINEON
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
module family are low profile SO-DIMM modules with
30,0 mm height based on DDR2 technology. DIMMs
are available as Non-ECC modules in 32M × 64
(256 MByte),64M × 64 (512 MByte) and 128M × 64
(1 GByte) organisation and density, intended for
mounting into 200-pin connector sockets.
The memory array is designed with 512Mb Double-
Data-Rate-Two (DDR2) Synchronous DRAMs.
Decoupling capacitors are mounted on the PCB board.
The DIMMs feature serial presence detect based on a
serial E²PROM device using the 2-pin I²C protocol. The
first 128 bytes are programmed with configuration data
and are write protected; the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 0.91, 2004-06
09122003-FTXN-KM26