HYS64T32000GDL Datasheet, PDF (22/48 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Module

HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
I_DD Specifications and Conditions
4.1
I_DD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 15 are used.
Table 15 I_DD Measurement Test Condition
Parameter
Symbol
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
CL_min
t_CKmin
t_RCDmin
t_RCmin
t_RRDmin
t_RASmin
t_RASmax
t_RPmin
t_RFCmin
t_REFI
-3.7
-5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
4
3
t_CK
3.75
5
ns
15
15
ns
60
55
ns
10
10
ns
45
40
ns
70000
70000
ns
15
15
ns
105
105
ns
7.8
7.8
µs
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
Table 16 ODT current per terminated pin
Parameter
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
Symbol
I_ODTO
I_ODTT
Min.
5
2.5
10
5
Typ.
6
3
12
6
Max.
7.5
3.75
15
7.5
Unit
mA/DQ
mA/DQ
mA/DQ
mA/DQ
EMRS(1) State
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
A6 = 1, A2 = 0
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 0.91, 2004-06
09122003-FTXN-KM26