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HYS64T32000GDL Datasheet, PDF (20/48 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Module
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HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 12 IDD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 13 IDD Specification HYS64T[32000/64020][G/H]DL
Product Type
Unit Notes
Organization 256 MB 256 MB 512 MB 512 MB 256 MB 256 MB 512 MB 512 MB
×64
×64
×64
×64
×64
×64
×64
×64
1 Rank 1 Rank 2 Ranks 2 Ranks 1 Rank 1 Rank 2 Ranks 2 Ranks
Symbol
Max. Max. Max. Max. Max. Max. Max. Max.
IDD0
280
280
300
300
320
320
340
340
mA 1)2)
IDD1
300
300
320
320
360
360
380
380
mA 1)2)
IDD2P
20
20
30
30
20
20
30
30
mA 1)3)
IDD2N
130
130
260
260
160
160
320
320
mA 1)3)
IDD2Q
100
100
200
200
120
120
240
240
mA 1)3)
IDD3P( MRS = 0)
50
50
100
100
60
60
130
130
mA 1)3)
IDD3P( MRS = 1)
20
20
40
40
20
20
40
40
mA 1)3)
IDD3N
140
140
280
280
160
160
320
320
mA 1)3)
IDD4R
340
340
360
360
400
400
420
420
mA 1)2)
IDD4W
360
360
380
380
440
440
460
460
mA 1)2)
IDD5B
480
480
500
500
520
520
540
540
mA 1)2)
IDD5D
20
20
50
50
20
20
50
50
mA 1)3)
IDD6
20
20
30
30
20
20
30
30
mA 1)4)
IDD7
840
840
860
860
880
880
900
900
mA 1)2)
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
4) standard
Data Sheet
20
Rev. 0.91, 2004-06
09122003-FTXN-KM26
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