HYS64T32000GDL Datasheet, PDF (19/48 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Module

HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
I_DD Specifications and Conditions
4
I_DD Specifications and Conditions
Table 12 I_DD Measurement Conditions¹⁾²⁾
Parameter
Symbol
Operating Current 0
I_DD0
One bank Active - Precharge; t_CK = t_CKmin., t_RC = t_RCmin., t_RAS = t_RASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
I_DD1
One bank Active - Read - Precharge; I_OUT = 0 mA, BL = 4, t_CK = t_CKmin., t_RC = t_RCmin., t_RAS = t_RASmin.,
t_RCD = t_RCDmin.,AL = 0, CL = CL_min.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I_DD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
I_DD2N
Precharge Quiet Standby Current
I_DD2Q
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; t_CK = t_CKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
I_DD3P(0)
Active Power-Down Current
All banks open; _tCK = t_CKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
I_DD3P(1)
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I_DD3N
I_DD4R
I_DD4W
Burst Refresh Current
I_DD5B
t_CK = t_CKmin., Refresh command every t_RFC = t_RFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
I_DD5D
t_CK = t_CKmin., Refresh command every t_RFC = t_REFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
19
Rev. 0.91, 2004-06
09122003-FTXN-KM26