HYB39S256400D Datasheet, PDF (6/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Overview
1
Overview
1.1
Features
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (x4, x8)
• Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7,8 µs)
• Random Column Address every CLK (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages: P–TSOPII–54 400mil width (x4, x8, x16)
• Chipsize Packages: P–TFBGA–54 (12 mm x 8 mm)
Table 1 Performance
Part Number Speed Code
–6
Speed Grade
PC166 3–3–3
max. Clock Frequency
@CL3 f_CK3 166
t_CK3 6
t_AC3 5
@CL2 t_CK2 7.5
t_AC2 5.4
–7
PC133 2–2–2
143
7
5.4
7.5
5.4
-7.5
PC133 3–3–3
133
7.5
5.4
10
6
–8
PC100 2–2–2
125
8
6
10
6
Unit
—
MHz
ns
ns
ns
ns
1.2
Description
The HYB39S256[40/80/16]0D[C/T](L) are four bank Synchronous DRAM’s organized as 4 banks x 16 MBit x4,
4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data
transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm
256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge
of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher
rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst
length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V
power supply. All 256-Mbit components are available in P–TSOPII–54 and P–TFBGA–54 packages.
Data Sheet
6
Rev. 1.02, 2004-02
10072003-13LE-FGQQ