HYB39S256400D Datasheet, PDF (22/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Electrical Characteristics
Table 14
Symbol
I_DD Specifications and Conditions¹⁾
-6
-7
-7.5 -8
Unit Note/ Test Condition
max.
I_DD1
t_RC = t_RC(min), I_O = 0 mA
100 80
80
80
mA
2)3)
I_DD2P
CS =V_{IH (min.)}, CKE ≤V_IL(max)
2
2
2
2
mA
2)
I_DD2N
CS =V_{IH (min.)}, CKE≥ V_IH(min)
35
30
30
25
mA
2)
I_DD3N
CS = V_IH(min), CKE ≥V_IH(min.)
40
35
35
30
mA
2)
I_DD3P CS = V_IH(min), CKE ≤ V_IL(max.)
5
5
5
5
mA
2)
I_DD4
110 90
90
70
mA
2)3)
I_DD5
t_RFC= t_RFC(min)
220
190
190
160
mA
4)
t_RFC= 7.8 µs
3
3
3
3
mA
I_DD6
x4, x8, x16
standard
3
3
3
3
mA
components 1.5 1.5 1.5 1.5 mA
low power
0.85 0.85 0.85 0.85 mA
components
1) T_A = 0 to 70 °C; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V
2) These parameters depend on the cycle rate. All values are measured at 166 MHz for -6, at 133 MHz for
-7 and -7.5 and at 100 MHz for -8 components with the outputs open. Input signals are changed once during t_CK.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is
assumed and the V_DDQ current is excluded.
4) t t _RFC= _RFC(min) “burst refresh”, t_RFC= 7.8 µs “distributed refresh”.
Data Sheet
22
Rev. 1.02, 2004-02
10072003-13LE-FGQQ