HYB39S256400D Datasheet, PDF (11/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

2.4
Block Diagrams
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Pin Configuration
C olum n Address
C ounter
C olum n Addresses
A 0 - A 9 , A 1 1 , A P,
BA0, BA1
C olum n Address
B uffe r
R ow Addresses
A0 - A12,
BA0, BA1
R ow Address
B u ffe r
Refresh Counter
Row
Decoder
M em ory
A rray
Bank 0
8196
x 2048
x 4 Bit
Row
Decoder
M em ory
A rray
Bank 1
8192
x 2048
x 4 Bit
Row
Decoder
M em ory
A rray
Bank 2
8192
x 2048
x 4 Bit
Row
Decoder
M em ory
A rray
Bank 3
8192
x 2048
x 4 B it
In p ut B u ffer O u tpu t B uffe r
DQ0 - DQ3
C ontrol Logic &
Tim ing G enerator
Figure 2 Block Diagram for 64M x 4 SDRAM (13/11/2 addressing)
S P B 041 27_2
Data Sheet
11
Rev. 1.02, 2004-02
10072003-13LE-FGQQ