HYB39S256400D Datasheet, PDF (23/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Electrical Characteristics
4.2
AC Characteristics
Table 15 AC Timing - Absolute Specifications –8/-7.5/–7/-6 ¹⁾²⁾³⁾
Parameter
Symbol
–8
–7.5
–7
–6
Unit Notes
PC100 -
222
PC166 -
333
PC166 -
222
PC166 -
333
min. max. min. max. min. max. min. max
.
Clock and Clock Enable
Clock Cycle Time
t_CK
CAS Latency = 3
CAS Latency = 2
Clock Frequency
t_CK
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
t_AC
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
t_CH
Clock Low Pulse Width
t_CL
Transition time
t_T
Setup and Hold Times
Input Setup Time
t_IS
Input Hold Time
t_IH
CKE Setup Time
t_CK
CKE Hold Time
t_CKH
Mode Register Set-up to Active t_RSC
delay
Power Down Mode Entry Time t_SB
Common Parameters
Row to Column Delay Time
t_RCD
Row Precharge Time
t_RP
Row Active Time
t_RAS
Row Cycle Time
t_RC
Row Cycle Time during Auto
t_RFC
Refresh
Activate(a) to Activate(b)
t_RRD
Command period
CAS(a) to CAS(b) Command
t_CCD
period
8—
10 —
7.5 —
10 —
7—
7.5 —
6 — ns
7.5 — ns
— 125 — 133 — 143 — 166 MHz
— 100 — 100 — 100 — 133 MHz
—6
—6
— 5.4 — 5.4 — 5
ns
3)4)5)
—6
— 5.4 — 5.4 ns
3—
3—
0.5 10
2.5 —
2.5 —
0.3 1.2
2.5 —
2.5 —
0.3 1.2
2 — ns
2 — ns
0.3 1.2 ns
2 — 1.5 — 1.5 — 1.5 — ns ⁶⁾
1 — 0.8 — 0.8 — 0.8 — ns ⁶⁾
2 — 1.5 — 1.5 — 1.5 — ns ⁶⁾
1 — 0.8 — 0.8 — 0.8 — ns ⁶⁾
2 — 2 — 2 — 2 — CLK
08
0 7.5 0 7
0 6 ns
20 — 20 — 15 — 15 — ns ⁷⁾
20 — 20 — 15 — 15 — ns ⁷⁾
48 100k 45 100k 37 100k 36 100k ns ⁷⁾
70 — 67 — 60 — 60 — ns ⁷⁾
70 — 67 — 63 — 60 — ns
16 — 15 — 14 — 12 — ns ⁷⁾
1 — 1 — 1 — 1 — CLK
Refresh Cycle
Data Sheet
23
Rev. 1.02, 2004-02
10072003-13LE-FGQQ