HYB39S256400D Datasheet, PDF (14/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Functional Description
3
Functional Description
3.1
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive
edge of the clock. The following list shows the truth table for the operation commands.
Table 7 Truth Table: Operation Command
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with
Autoprecharge
Read
Read with
Autoprecharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Device State
Idle³⁾
Any
Any
Active³⁾
Active³⁾
CKE
n-1¹⁾²⁾
H
H
H
H
H
Active³⁾
H
Active³⁾
H
Idle
H
Any
H
Active
H
Any
H
Idle
H
Idle
H
Idle (Self Refr.) L
Clock Suspend Entry Active
H
Power Down Entry Idle
H
(Precharge or active
standby)
Active
Clock Suspend Exit Active⁴⁾
L
Power Down Exit Any (Power L
Down)
Data Write/Output Active
H
Enable
Data Write/Output Active
H
Disable
CKE
n¹⁾²⁾
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
DQM BA0 AP= Addr. CS RAS CAS WE
1)2)
BA1¹⁾²⁾ A10^{1)2) 1)2)}
1)2) 1)2) 1)2) 1)2)
XV
V
V LL H H
XV
L
X
LL H L
XX
H
X
LL H L
XV
L
V LH L L
XV
H
V LH L L
XV
L
V LH L H
XV
H
V LH L H
XV
V
V LL L L
XX
X
X LH H H
XX
X
X
LH H L
XX
X
X HX X X
XX
X
X LL L H
XX
X
X LL L H
XX
X
X HX X X
LH H X
XX
X
X XX X X
XX
X
X HX X X
LH H H
XX
X
X XX X X
XX
X
X HX X X
LH H L
L
X
X
X XX X X
HX
X
X XX X X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
clock suspend mode.
Data Sheet
14
Rev. 1.02, 2004-02
10072003-13LE-FGQQ