HYB39S256400D Datasheet, PDF (13/28 Pages) Infineon Technologies AG – 256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Pin Configuration
Column Address
Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
Figure 4 Block Diagram for 16M x 16 SDRAM (13/9/2 addressing)
SPB04129
Data Sheet
13
Rev. 1.02, 2004-02
10072003-13LE-FGQQ