SAK-XE167FM-72F80LAA Datasheet, PDF (53/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Functional Description
3
Functional Description
The architecture of the XE167xM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 4). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XE167xM.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE167xM.
PSRAM
Flash
Memory
System Functions
Clock, Reset, Power
Control, StandBy RAM
DPRAM
DSRAM
CPU
MAC Unit
MPU
Interrupt & PEC
Interrupt Bus
OCDS
Debug Support
EBC
LXBus Control
External Bus
Control
MCHK
WDT
RTC
ADC0 ADC1
Module Module
GPT
CC2 CCU6 x
Modules Modules
USICx
Modules
10 -Bit 10 -Bit
8-Bit 8-Bit
5
Timers
16
Chan.
3+1
Chan.
each
2
Chan.
each
Analog and Digital General Purpose IO (GPIO) Ports
Multi
CAN
Shared
MOs
for
Nodes
Figure 4 Block Diagram
Data Sheet
53
MC_BL_BLOCKDIAGRAM
V2.1, 2011-07