SAK-XE167FM-72F80LAA Datasheet, PDF (121/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Electrical Parameters
Table 29 EBC External Bus Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Output valid delay for RD, t₁₀ CC −
7
13
ns
WR(L/H)
Output valid delay for
t₁₁ CC −
7
14
ns
BHE, ALE
Address output valid delay t₁₂ CC −
8
14
ns
for A23 ... A0
Address output valid delay t₁₃ CC −
8
15
ns
for AD15 ... AD0 (MUX
mode)
Output valid delay for CS t₁₄ CC −
7
13
ns
Data output valid delay for t₁₅ CC −
8
15
ns
AD15 ... AD0 (write data,
MUX mode)
Data output valid delay for t₁₆ CC −
8
15
ns
D15 ... D0 (write data,
DEMUX mode)
Output hold time for RD, t₂₀ CC -2
6
8
ns
WR(L/H)
Output hold time for BHE, t₂₁ CC -2
6
ALE
10
ns
Address output hold time t₂₃ CC -3
6
8
ns
for AD15 ... AD0
Output hold time for CS t₂₄ CC -3
6
Data output hold time for t₂₅ CC -3
6
D15 ... D0 and AD15 ...
AD0
11
ns
8
ns
Input setup time for
t₃₀ SR 25
15
−
ns
READY, D15 ... D0, AD15
... AD0
Input hold time READY, t₃₁ SR 0
-7
−
ns
D15 ... D0, AD15 ... AD0¹⁾
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
121
V2.1, 2011-07